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cml semiconductor products ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc d/828/4 august 2009 1.0 features provisional issue ? fast ctcss detection ? programmable tone decoder ? full 23/24 bit dcs codec ? programmable comparator for rssi ? non-predictive tone detection ? programmable modulator drivers ? low power 3.3v/5v operation ? programmable tone encoders ? variable gain audio filter ? full duplex ctcss and selcall 1.1 brief description the fx828 is an innovative ctcss, dcs and selca ll codec, designed for the latest generation of land mobile radio equipment. designed to complement the fx829, the fx828 has many advanced features which assist the operation of modern subaudio and inband based si gnalling systems. the fx828 is electrically, physically and software compatible with the fx818 and fx829. it permits manufacturers to add new features to their equipment with minimal design changes. the fx828 incorporates a programmable tone decoder which can be set to respond to between 1 and 15 ctcss or selcall tones with minimum software interv ention. in addition, a 'fast' ctcss detector can respond to a single programmed tone in 60 ms, or can be used to provide an output if any ctcss tone is present at the detector input. two high resoluti on tone encoders perform accurate generation of any ctcss or selcall tone in current use. full 23 or 24 bit dcs encoding and decoding complements the ctcss/selcall line-up. a timer is included whic h, for example, may be used for timing selcall transmissions and a comparator is provided to assist with carrier or rssi monitoring. the device can operate full duplex in all operating modes except for dcs. the fx828 along with the fx818 and fx829 is offered in a choice of small ssop, dil and soic 24-pin packages. it may be used with 3.0 to 5.5 volt supply.
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 2 d/828/4 contents section page 1.0 features ................................................................................................ 1 1.2 block diagram .................................................................................... 3 1.3 signal list ............................................................................................ 4 1.3 signal list ............................................................................................ 4 1.4 external components ..................................................................... 6 1.4 external co mponents............................................................................. 6 1.5 general description ......................................................................... 7 1.5.1 software description ................................................................. 7 1.6 application notes ........................................................................... 20 1.6.1 general ...................................................................................... 20 1.6.2 transmitter ............................................................................... 20 1.6.3 receiver (decode) .................................................................... 21 1.6.4 receiver (fast detect) ............................................................. 21 1.6.5 receiver (dcs decoder) .......................................................... 21 1.6.6 general purpose timer ........................................................... 22 1.6.7 full duplex modes ................................................................... 22 1.6.8 tx / fast rx tone table ........................................................... 23 1.6.9 rx program tone table ........................................................... 23 1.6.10 tx tone program table : selcall ............................................ 24 1.6.11 rx tone program table : selcall ............................................ 25 1.6.12 tx dcs code table .................................................................... 26 1.7 performance specification ......................................................... 27 1.7.1 electrical performance ............................................................ 27 1.7.2 packaging ................................................................................. 33
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 3 d/828/4 1.2 block diagram figure 1 block diagram
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 4 d/828/4 1.3 signal list package d2/d5/p4 signal description pin no. name type 1 xtaln o/p the inverted output of the on-chip oscillator. 2 xtal/clock i/p the input to the on-chip oscillator, for external xtal circuit or clock. 3 serial clock i/p the "c-bus" serial clock input. this clock, produced by the controller, is used for transfer timing of commands and data to and from the device. see "c-bus" timing diagram (figure 4). 4 command data i/p the "c-bus" serial data input from the controller. data is loaded into this device in 8-bit bytes, msb (b7) first, and lsb (b0) last, synchronised to the serial clock. see "c-bus" timing diagram (figure 4). 5 reply data o/p the "c-bus" serial data output to the controller. the transmission of reply data bytes is synchronised to the serial clock under the control of the csn input. this 3-state output is held at high impedance when not sending data to the controller. see "c-bus" timing diagram (figure 4). 6 csn i/p the "c-bus" data l oading control function: this input is provided by the controller. data transfer sequences are initiated, completed or aborted by the csn signal. see "c-bus" timing diagram (figure 4). 7 irqn o/p this output indicates an interrupt condition to the controller by going to a logic "0". this is a "wire-orable" output, enabling the connection of up to 8 peripherals to 1 interrupt port on the controller. this pin has a low impedance pulldown to logic "0" when active and a high- impedance when inactive. an external pullup resistor is required. the conditions that cause interrupts are indicated in the irq flag register and are effective if not masked out by a corresponding bit in the irq mask register.
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 5 d/828/4 1.3 signal list (continued) package d2/d5/p4 signal description pin no. name type 8 compout o/p the output of the comparator. 9 compin i/p the input to the comparator. 10 a/d cap 1 o/p an internal reference voltage for the ctcss a to d. decouple to v ss with an external capacitor. 11 a/d cap 2 o/p an internal reference voltage for the dcs a to d. decouple to v ss with an external capacitor. 12 v ss power the negative supply rail (ground). 13 v bias o/p a bias line for the internal circuitry, held at ? v dd . this pin must be decoupled by a capacitor mounted close to the device pins. 14 rx amp in i/p the inverting input to the rx input amplifier. 15 rx amp out o/p the output of the rx input amplifier and the input to the audio filter section. 16 rx audio out o/p output of the rx audio filter section. 17 tx audio out o/p output of the selcall tone generator. 18 sum in i/p input to the audio summing amplifier. 19 sum out o/p output of the audio summing amplifier. 20 mod1 in i/p input to mod1 audio gain control. 21 tx sub audio out o/p output of the ctcss or dcs tx tone generator. 22 mod1 o/p output of mod1 audio gain control. 23 mod2 o/p output of mod2 audio gain control. 24 v dd power the positive supply rail. levels and voltages are dependent upon this supply. this pin should be decoupled to v ss by a capacitor. notes: i/p = input o/p = output
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 6 d/828/4 1.4 external components c1 22pf 20% r1 1m 5% x1 4.032mhz c2 22pf 20% r2 100k 10% (tolerance depends upon c3 100pf 20% r3 100k 10% system requirements) c4 0.1f 20% r4 note 2 10% c5 100pf 20% r5 22k 10% c6 0.1f 20% r6 note 1 10% c7 note 2 20% r7 note 1 10% c8 0.1f 20% c9 1.0 to 3.3f 20% notes : 1. r2, r6, r7 and c3 form the gain components for the summing amplifier. r6 and r7 should be chosen as required from the system specification, using the following formula: tx sub audio gain = ? r2 r6 tx audio gain = ? r2 r7 2. r3, r4, c5 and c7 form the gain components for the rx input amplifier. r4 should be chosen as required by the signal level, using the following formula: gain = ? r3 r4 c7 x r4 should be chosen so as not to compromise the low frequency performance of this product. figure 2 recommended external components
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 7 d/828/4 1.5 general description the fx828 is a signalling encoder/decoder for use in land mobile radio equipment, see figure 1. the transmitter section of this device has independently controllable tone generators for sub- audio (ctcss) and inband (selcall) signalling. it al so features a dcs code generator, which may be used in place of the ctcss tone generator. the receiver section of the fx828 has a fast/p redictive ctcss tone detector which operates in parallel with a dcs decoder and a ctcss/selcall tone decoder. the latter is switchable to perform either ctcss or selcall tone decoding of a user-programmable set of up to 15 tones. in the ctcss mode it performs a more accurate (but slower) analysis of the tones detected by the fast/predictive ctcss tone detector, which is a single detector that is switchable to provide either a fast response to any ctcss tone (fast detect mode) or a fast response to a single user- programmed ctcss tone (predictive mode). other functions on the fx828 are a comparator with programmable threshold level, a general purpose timer and a summing amplifier with two adjustable gain blocks, which may be used for two point modulation, for example. all fx828 func tions are controlled by an external c over the c-bus interface, a serial interface designed to reduce interference levels in radio equipment. 1.5.1 software description address/commands instructions and data are transferred, via "c-bus ", in accordance with the timing information given in figure 4. instruction and data transactions to and from the fx828 consist of an address/command (a/c) byte followed by either: (i) a further instruction or data (1 or 2 bytes) or (ii) a status or rx data reply (1 byte)
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 8 d/828/4 8-bit write only registers hex address/ command register name bit 7 (d7) bit 6 (d6) bit 5 (d5) bit 4 (d4) bit 3 (d3) bit 2 (d2) bit 1 (d1) bit 0 (d0) $01 general n/a n/a n/a n/a n/a n/ a n/a n/a reset subaudio tone fast selcall dcs $80 signalling tx decoder detect tx rx control enable enable enable 0 0 enable 0 enable tone decoder bandwidth fast ctcss $82 signalling msb lsb mode tone subaudio dcs set-up bit 3 bi t 2 bit 1 bit 0 detect/ predictive decoder mode tx mode 23/24 dcs byte 3 $85 dcs optional msb byte 3 bit 23 bit 22 bit 21 bi t 20 bit 19 bit 18 bit 17 bit 16 dcs byte 2 $86 dcs byte 2 bit 15 bit 14 bit 13 bi t 12 bit 11 bit 10 bit 9 bit 8 dcs byte 1 $87 dcs lsb byte 1 bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 bpf msb lsb $88 general bpf bpf 6db dac da c dac gp timer gp timer control enable un-mute pad bit 2 bit 1 bit 0 enable re-cycle general general purpose timer $8b purpose msb lsb timer bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gp timer comp comp tone ctcss dcs $8e irq 0 irq 0 to 1 1 to 0 irq fast irq 0 irq mask mask irq mask irq mask mask mask mask $9c reserved for later use
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 9 d/828/4 16-bit write only registers hex address/ command register name bit 7 (d7) bit 6 (d6) bit 5 (d5) bit 4 (d4) bit 3 (d3) bit 2 (d2) bit 1 (d1) bit 0 (d0) ctcss tx/ ctcss tx/fast rx frequency $83 fast rx ctcss (tx) 0 0 msb frequency (1) notone bit 12 bit 11 bit 10 bit 9 bit 8 ctcss tx/ ctcss tx/fast rx frequency fast rx lsb frequency (2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rx tone tone address tone frequency $84 program msb lsb msb (1) bit 3 bit 2 bit 1 bit 0 bit 11 bit 10 bit 9 bit 8 rx tone tone frequency program lsb (2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 audio mod 1 $8a control 0 0 mod 1 msb lsb (1) enable bit 4 bi t 3 bit 2 bit 1 bit 0 audio mod 2 control 0 0 mod 2 msb lsb (2) enable bit 4 bi t 3 bit 2 bit 1 bit 0 selcall tx tone $8d selcall tx selcall 0 0 msb (1) notone bit 12 bit 11 bit 10 bit 9 bit 8 selcall tx tone selcall tx lsb (2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 10 d/828/4 write only register description general reset (hex address $01) the reset command has no data attached to it. it se ts the device registers into the specific (all powersaved) states as listed below: register name hex address bit 7 (d7) bit 6 (d6) bit 5 (d5) bit 4 (d4) bit 3 (d3) bit 2 (d2) bit 1 (d1) bit 0 d0) signalling control $80 0 0 0 0 0 0 0 0 selcall & sub-audio status $81 0 0 0 0 x x x x signalling set-up $82 0 0 0 0 0 0 0 0 ctcss tx / fast rx frequency (1) $83 0 0 0 0 0 0 0 0 ctcss tx / fast rx frequency (2) 0 0 0 0 0 0 0 0 rx tone program (1) $84 0 0 0 0 0 0 0 0 rx tone program (2) 0 0 0 0 0 0 0 0 dcs byte 3 $85 0 0 0 0 0 0 0 0 dcs byte 2 $86 0 0 0 0 0 0 0 0 dcs byte 1 $87 0 0 0 0 0 0 0 0 general control $88 0 0 0 0 0 0 0 0 audio control (1) $8a 0 0 0 0 0 0 0 0 audio control (2) 0 0 0 0 0 0 0 0 general purpose timer $8b 0 0 0 0 0 0 0 0 selcall tx (1) $8d 0 0 0 0 0 0 0 0 selcall tx (2) 0 0 0 0 0 0 0 0 irq mask $8e 0 0 0 0 0 0 0 0 irq flag $8f 0 0 0 0 0 0 0 0 x = undefined signalling control register (hex address $80) this register is used to control the f unctions of the device as described below: subaudio tx enable (bit 7) bit 7 should be set to ?1? to enable the ctcss/dcs subaudio transmitter. the subaudio tx type will depend on the state of the subaudio tx mode (bit 1 signalling set-up register $82). tone decoder enable (bit 6) bit 6 should be set to ?1? to enable the ctcss/selcall tone decoder or the dcs decoder. note: see also bit 0 for dcs decoder operation. bits 7 and 6 should not both be set to ?1? when bit 0 is set to ?1? because the dcs function is half-duplex only. ctcss fast detect enable (bit 5) when this bit is "1", the fast ctc ss detect or fast ctcss predictive mode is enabled, depending upon the setting of fast ctcss mode (bit 3 signalling set-up register, $82). when this bit is "0", both fast ctcss detect and fast ctcss predicti ve tone detectors are disabled. selcall tx enable (bit 2) when this bit is "1" the se lcall transmitter is enabled. when this bit is "0" the selcall transmitter is disabled and powersaved. dcs rx enable (bit 0) when this bit is "1" and bit 6 is ?1?, the dcs decoder is enabled. when this bit is "0" the dcs decoder is disabled. the dcs decoder and the subaudio (ctcss or dcs) transmitter should not be enabled at the same time. (bits 4, 3, and 1) reserved for future use. these bits should be set to "0".
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 11 d/828/4 signalling set-up register (hex address $82) this register is used to define the signalling parameters, as described below: tone decoder bandwidth (bits 7, 6, 5 and 4) these four bits set the bandwidth of the ctcss/selcall tone decoder according to the table below: bandwidth bit 7 bit 6 bit 5 bit 4 will decode will not decode recommended for ctcss 1 0 0 0 1.1% 2.4% recommended for ccir 1 0 0 1 1.3% 2.7% 1 0 1 0 1.6% 2.9% 1 0 1 1 1.8% 3.2% 1 1 0 0 2.0% 3.5% 1 1 0 1 2.2% 3.7% recommended for zvei 1 1 1 0 2.5% 4.0% 1 1 1 1 2.7% 4.2% fast ctcss mode (bit 3) when ctcss fast detect enable (bit 5 signalling control register, $80) is "1", this bit select s the fast ctcss detect or the fast ctcss predictive mode, according to the table below: detect/ predictive bit 3 function 0 detect mode 1 predictive mode if the ctcss fast detect enable bit is "0" then both modes are deselected. tone decoder mode (bit 2) when this bit is "1" the ctcss/selc all tone decoder is set to detect inband (selcall) tones. when this bit is "0" the tone decoder is set to detect subaudio (ctcss) tones. subaudio tx mode (bit 1) when this bit is "1" the subaudio transmi tter will be set to transmit dcs signals, if enabled. when this bit is "0" the subaudio transmitter will be set to transmit ctcss signals, if enabled. dcs 23/24 (bit 0) when this bit is "1" the dcs transmitte r and decoder are configured for a 23-bit code. when this bit is "0" they are configured for a 24-bit code. dcs byte 3 register (hex address $85) dcs byte 2 register (hex address $86) dcs byte 1 register (hex address $87) these three bytes set the code that is transmitted or received in the dcs mode. the lsb bit 0 of the dcs byte 1 is transmitted first and the last bit is t he msb bit 23 of dcs byte 3 in the 24-bit mode or bit 22 in the 23-bit mode.
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 12 d/828/4 general control register (hex address $88) this register is used to control the f unctions of the device as described below: bpf enable (bit 7) when this bit is "1" the audio band-pass filter is enabled. when this bit is "0" the audio band-pass filter is disabled (powersaved). bpf un-mute (bit 6) when this bit is "1" the audio band-pass f ilter output is switched to the rx audio out pin. when this bit is "0" the output of the filter is disconnected from rx audio out, which is t hen in a high impedance state. this control, along with bpf enable, a llows the filter to power up and settle internally before switching the output on, to avoid clicks when coming out of powersave. bpf 6db pad (bit 5) when this bit is "1" a 6db attenuator is inserted into the output of the audio band-pass filter. when this bit is "0" t he output of the audio band-pass filter is not attenuated. dac (bits 4, 3 and 2) these three bits set the level of the di gital to analogue converter that feeds the negative input of the comparator. the dac can be set to one of eight levels equally spaced between v ss and v bias , not including v ss , but including v bias , i.e. with a 5v supply, the lowest level would be 312.5mv set by "000" in bits 2, 3 and 4 and the highest level would be 2.5v set by "111" in bits 2, 3 and 4. timer enable (bit 1) when this bit goes to a "1" the general pur pose timer is restarted and its internal register is re-loaded from the value specified in the general purpose timer register (hex address $8b). it will then count down from the count held in its internal register. when this bit is "0" the count down is disabled and the last pre-programmed value is retained in the timer's internal register. timer re-cycle (bit 0) when this bit is "1" the general purpose ti mer will re-load its internal register from the value specified in the ge neral purpose timer register (hex address $8b) when the count in the internal register reaches zero (i.e. the timeout has expired). it then restarts the count down, so that the timer continuously cycles. when this bit is "0" the general purpose timer will stop when the count in the internal register reaches zero (i.e. t he timeout has expired). the timer can only be restarted by reloading a value into the general purpose timer register (hex address $8b). if this bit is switched from "1" to "0" whilst the timer is enabled then the timer will complete the present count before stopping. general purpose timer (gpt ) register (hex address $8b) this register is used to preset the value of a countdown timer. once a binary value has been loaded into this register, it will be automatically transferred to an internal register within the timer. this internal register is then decremented at each count interval (1ms) until it reaches zero. on reaching zero, the gpt irq flag in the irq flag register (hex address $8f) is set to "1". an interrupt is generated on the irqn pin if the gpt irq mask in the irq mask register (hex address $8e) is "1" otherwise the gpt irq flag remains set to "1" and no interrupt is generated.
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 13 d/828/4 when the internal register has reached a count of zero, the action of the timer depends on the setting of the timer re-cycle bit in the general control register (hex address $88). if the timer re- cycle bit is "1" then the timer will re-load the countdown value from the general purpose timer register and restart the countdown from this value. if the time re-cycle bit is "0" then the timer will stop and no further action or timer interrupts w ill take place until the general purpose timer register is re-loaded. loading the ge neral purpose timer with "0" will cause the timer circuitry to be disabled (i.e. powersaved). irq mask register (hex address $8e) this register is used to control t he interrupts (irqs) as described below: (bits 7 and 1) reserved for future use. these should be set to "0". gpt irq mask (bit 6) when this bit is set to "1" it enables an interrupt that occurs when gpt irq flag (bit 6, irq flag regist er, $8f) changes from "0" to "1". when this bit is "0" t he interrupt is masked. comp 0 to 1 irq mask (bit 5) when this bit is set to "1" it enables an interrupt that occurs when the comparator output goes from "0" to "1". when this bit is set to "0" the interrupt is masked. comp 1 to 0 irq mask (bit 4) when this bit is set to "1" it enables an interrupt that occurs when the comparator output goes from "1" to "0". when this bit is set to "0" the interrupt is masked. tone irq mask (bit 3) when this bit is set to "1" it enables an interrupt that occurs when the tone irq flag (bit 3, irq flag register, $8f) changes from "0" to "1". when this bit is "0" t he interrupt is masked. ctcss fast irq mask (bit 2) when this bit is set to "1" it enables an interrupt that occurs when the ctcss fast irq flag (bit 2, ir q flag register, $8f) changes from "0" to "1". when this bit is "0" the interrupt is masked. dcs irq mask (bit 0) when this bit is set to "1" it enables an interrupt that occurs when the dcs decode/no decode flag (bit 7, selcall & sub-audio status register $81) changes state. when this bit is set to "0" the interrupt is masked. ctcss tx/fast rx frequency register (hex address $83) this is a 16-bit register. byte (1 ) is sent first. when the ctcss fast detector is enabled, the bits 0 to 12 define the receive frequency the fast predictive detector is looking for according to the formula below. when the ctcss transmitter is enabled, the bits 0 to 12 control the frequency of the transmitted ctcss tones according to the formula below. when the fast detector and the transmitter are both enabl ed, the bits 0 to 12 define the receive frequency the fast predictive detector is looking for and t he frequency of the transmitted tone according to the formula below (i.e. tx tone = predictive tone). a f (hz) 16 x f (hz) xtal tone = where a is the binary number programmed into the 13 bits.
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 14 d/828/4 when bit 7 in byte (1) is set to "1" the tone output is set at v bias or notone without regard to the number "a" programmed. when bit 7 is "0" the pr ogrammed tone is set on the output. programming the bits 0 to 12 to "0" puts the tx into powersave and the output goes to v bias . powersave is also achieved by disabling the subaudio tx and the ctcss fast detect. rx tone program register (hex address $84) this is a 16-bit register. byte (1 ) is sent first. the two bytes are used to program the centre frequencies of up to 15 tones in either the audio or sub-audio band that will be decoded by the receiver. each tone is identified by its address in bits 7, 6, 5 and 4 of byte (1). the remaining 12 bits contain the data representing the tone frequency according to the fo rmula below. if a tone is not required the 12 bits should be set to zero. byte 1 byte 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 <------------------------ n -----------------------> <----------------------- r ------------------------> 0 0 0 1 0 0 1 0 n is the binary representation of the r is the nearest 6-bit binary 0 0 1 1 following decimal number (n): representation of (r), where: 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 subaudio (ctcss) subaudio (ctcss) 1 0 0 0 n = int (948982 x f tone / f xtal ) r = ((237245/f xtal ) - (n/(4 x f tone ))) x 8400 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 inband (selcall) inband (selcall) 1 1 0 1 n = int (83036 x f tone / f xtal ) r = ((20759/f xtal ) - (n/(4 x f tone ))) x 96000 1 1 1 0 example: to program 100hz when using the recommended 4.032mhz xtal in subaudio (ctcss) mode. n = int (948982 x 100 / 4.032 x 10^6) = int (23.536) = 23 n = 010111 (binary) r = ((237245 / 4.032 x 10^6) - (23 / (4 x 100))) x 8400 = 11.26 (round up if exactly halfway) r = 11 = 001011 (binary) thus the 12-bit code is 010111001011 the hex address represented by bits 7, 6, 5 and 4 in byte (1) is used as the code to indicate which tone has been decoded. this code appears in bits 3, 2, 1 and 0 of the selcall and sub-audio status register (hex address $81). the 15 programmed tones use hex addresses $0 - $e.
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 15 d/828/4 audio control register (hex address $8a) this is a 16-bit register. byte (1) is sent first. bits 0 - 5 of the first byte in this register are used to set the attenuation of the modulator 1 amplifier and bits 0 - 5 of the second byte in this register are used to set the attenuation of the modulator 2 amplif ier, according to the tables below: byte 1 byte 2 5 4 3 2 1 0 mod. 1 attenuation 5 4 3 2 1 0 mod. 2 attenuation 0 x x x x x disabled (v bias ) 0 x x x x x disabled (v bias ) 1 0 0 0 0 0 >40db 1 0 0 0 0 0 >40db 1 0 0 0 0 1 12.0db 1 0 0 0 0 1 6.0db 1 0 0 0 1 0 11.6db 1 0 0 0 1 0 5.8db 1 0 0 0 1 1 11.2db 1 0 0 0 1 1 5.6db 1 0 0 1 0 0 10.8db 1 0 0 1 0 0 5.4db 1 0 0 1 0 1 10.4db 1 0 0 1 0 1 5.2db 1 0 0 1 1 0 10.0db 1 0 0 1 1 0 5.0db 1 0 0 1 1 1 9.6db 1 0 0 1 1 1 4.8db 1 0 1 0 0 0 9.2db 1 0 1 0 0 0 4.6db 1 0 1 0 0 1 8.8db 1 0 1 0 0 1 4.4db 1 0 1 0 1 0 8.4db 1 0 1 0 1 0 4.2db 1 0 1 0 1 1 8.0db 1 0 1 0 1 1 4.0db 1 0 1 1 0 0 7.6db 1 0 1 1 0 0 3.8db 1 0 1 1 0 1 7.2db 1 0 1 1 0 1 3.6db 1 0 1 1 1 0 6.8db 1 0 1 1 1 0 3.4db 1 0 1 1 1 1 6.4db 1 0 1 1 1 1 3.2db 1 1 0 0 0 0 6.0db 1 1 0 0 0 0 3.0db 1 1 0 0 0 1 5.6db 1 1 0 0 0 1 2.8db 1 1 0 0 1 0 5.2db 1 1 0 0 1 0 2.6db 1 1 0 0 1 1 4.8db 1 1 0 0 1 1 2.4db 1 1 0 1 0 0 4.4db 1 1 0 1 0 0 2.2db 1 1 0 1 0 1 4.0db 1 1 0 1 0 1 2.0db 1 1 0 1 1 0 3.6db 1 1 0 1 1 0 1.8db 1 1 0 1 1 1 3.2db 1 1 0 1 1 1 1.6db 1 1 1 0 0 0 2.8db 1 1 1 0 0 0 1.4db 1 1 1 0 0 1 2.4db 1 1 1 0 0 1 1.2db 1 1 1 0 1 0 2.0db 1 1 1 0 1 0 1.0db 1 1 1 0 1 1 1.6db 1 1 1 0 1 1 0.8db 1 1 1 1 0 0 1.2db 1 1 1 1 0 0 0.6db 1 1 1 1 0 1 0.8db 1 1 1 1 0 1 0.4db 1 1 1 1 1 0 0.4db 1 1 1 1 1 0 0.2db 1 1 1 1 1 1 0db 1 1 1 1 1 1 0db x = don't care mod1 enable (bit 5, first byte) when this bit is "1" the mod1 attenuator is enabled. when this bit is "0" the mod1 att enuator is disabled (i.e. powersaved). mod2 enable (bit 5, second byte) when this bit is "1" the mod2 att enuator and the summing amp are enabled. when this bit is "0" they are both disabled (i.e. powersaved). (bits 7 and 6, first and second bytes) reserved for future use. these should be set to "0". selcall tx register (hex address $8d) this is a 16-bit register. byte (1) is sent first. when the selcall transmitter is enabled, bits 0 to 12 control the frequency of the transmitted selcall tones according to the formula overleaf:
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 16 d/828/4 a f (hz) 4 x f (hz) xtal tone = where a is the binary number programmed into the 13 bits. when bit 7 (in the first 8 bits) is set to "1" the tone output is set at v bias or notone without regard to the number "a" programmed. when bit 7 is "0" the pr ogrammed tone is set on the output. programming the bits 0 to 12 to "0" puts the tx into powersave and the output goes to v bias . powersave is also achieved by disabling the selcall tx. 8-bit read only registers hex address/ command register name bit 7 (d7) bit 6 (d6) bit 5 (d5) bit 4 (d4) bit 3 (d3) bit 2 (d2) bit 1 (d1) bit 0 (d0) selcall & dcs ctcss rx tone $81 sub-audio decode/ fast 0 tone msb lsb status no decode tone decode bit 3 bit 2 bit 1 bit 0 gp timer comp comp tone ctcss fast dcs $8f irq flag 0 irq 0 to 1 1 to 0 irq irq 0 irq flag irq flag irq flag flag flag flag read only register description selcall and sub-audio status register (hex address $81) this register is used to indicate the status of the device as described below: dcs decode/no decode (bit 7) when the dcs decoder is enabled this bi t is continuously updated with the result. a "1" indicates a successful decode (with 3 or less errors). a "0" indicates a failure to decode. ctcss fast tone (bit 6) when bit 5 in the signalling control register and bit 3 in the signalling set-up register are set to enable fast ctcss detect mode, this bit will be set to "1" if a periodic tone is detected. if no periodic tone is detected this bit will be "0". when bits 5 and 3 are set to enable fast ctcss predictive mode, this bit will be set to "1" if a periodic tone t hat matches the frequency programmed in the ctcss tx/fast rx frequency regi ster is detected. if no match is found this bit will be "0". when bit 5 in the signalling control r egister is set to "0" this bit will be "0". (bit 5) reserved for future use. this will be set to "0" but should be ignored by the user's software. tone decode (bit 4) this bit indicates the status of the tone decoder. a "1" indicates a tone has been detected (tone decode) and a "0" indicates the loss of the tone (notone).
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 17 d/828/4 tone decode means that a tone has been decoded and its characteristics are defined by the bandwidth (see signalli ng set-up register bits 7, 6, 5 and 4) and the rx tone number (s ee selcall and sub-audio status register bits 3, 2, 1 and 0). when bit 6 in the signalling control register is set to "0" the tone decode bit 4 will be set to "0". identification of a valid tone which is not in the pre-programmed list of up to 15 tones will cause the decoder to move to the tone decode st ate with the rx tone address of "1111" in bits 3, 2, 1 and 0; indicating a valid, but unrecognised, tone. loss of tone, will c ause the notone timer to be started. if loss of tone continues for the duration of the timeout period, then the decoder will move to notone state and the ident ification of pre-programmed tones will start again. the time-out period is not user-adjustable. rx tone (bits 3, 2, 1 and 0) these four bits hold a hex number from $0 to $f. numbers $0 to $e represent the address of the tone decoded according to the tones programmed in the rx tone program register, $84. the hex number $f indicates the presence of any tone that is not described by decoder bandwidth (bits 7, 6, 5 and 4, signalling set-up register, $82) and frequency (bits 11 - 0, rx tone program register, $84). irq flag register (hex address $8f) this register is used to indicate when the device requires attention as below: (bits 7 and 1) reserved for future use. these will be set to "0" but should be ignored by user's software. gpt irq flag (bit 6) when the general purpose timer has reached zero in its internal register, this bit will be set to "1" to indicate the timeout has expired. this bit is cleared to "0" by a read of the irq flag register (hex address $8f). comp 0 to 1 irq flag (bit 5) when the comparator output goes from "0" to "1" (i.e. when the input voltage is above the dac output voltage) this bit will be set to "1" and an interrupt generated (if bit 5 of the irq mask register $8e is set to "1"). this bit is set to "0" when the irq flag register $8f is read. comp 1 to 0 irq flag (bit 4) when the comparator output goes from "1" to "0" this bit will be set to "1" and an interrupt generated (if bit 4 of the irq mask r egister $8e is set to "1"). this bit is set to "0" when the irq fl ag register $8f is read. tone irq flag (bit 3) when rx tone decode (bit 4, selcall and sub-audio status register, $81) or rx tone (the decoded 4 bit tone address in register $81) changes state this bit will be set to "1". th is bit is cleared to "0" by a read of the irq flag register (hex address $8f). ctcss fast irq flag (bit 2) when ctcss fast tone (bit 6, selcall and sub-audio status register, $81) changes state this bit will be se t to "1". this bit is cleared to "0" by a read of the irq flag register (hex address $8f). dcs irq flag (bit 0) when dcs decode/no decode (bit 7 selcall and sub-audio status register, $81) changes state this bit will be se t to "1". this bit is cleared to "0" by a read of the irq flag register (hex address $8f).
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 18 d/828/4 the flow chart shows the following modes of operation for the example below: 1. decode ) 2. decode and fast detect ) e.g. address 3 = 100hz, bandwidth = 2.7%, interrupt enabled 3. decode & fast predictive ) 4. transmit, e.g. tx = 100hz note: $8x is the hex address/command.
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 19 d/828/4 the flow chart shows the decoder, fast detect/fast predictive and transmitter enabled with the following example. 1. tx tone generator = 100hz 2. decoder programmed with 100hz in address 3 3. bandwidth setting = 2.7% 4. interrupt enabled note: $8x is the hex address/command.
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 20 d/828/4 1.6 application notes 1.6.1 general the fx828 is intended for use in radio systems wher e signalling is required for functions such as trunking, control, selective calling or group calling. the ctcss fast/predictive detector is useful for t he detection of occupied channels indicating either the presence of any sub-audio tone, or range of tones, depending if it is set in fast detect or predictive mode. this will increase the efficiency of scanning and trunki ng systems, reducing the av erage time allocated to assessing each channel. the facility to decode any of up to 15 programmed tones allows the use of tones for various signalling functions such as masking a free channel or i dentifying sub groups within a user's groups. adjustable decoder bandwidths permit certainty and signal to noise performance to be traded when congestion or range limits the system performance. 1.6.2 transmitters the ctcss transmitter is enabled with bit 7 in the signalling control register ($80) and bit 1 in the signalling set up register ($82). the tx frequency is set using bit 0 to bit 12 in the ctcss tx/fast rx frequency register ($83) using the formula below: a f (hz) 16 x f (hz) xtal tone = where a is the binary number programmed into the 13 bits. when bit 7 (in the first 8 bits) is set to "1" the tone output is set at v bias or notone without regard to the number "a" programmed. when bit 7 is "0" the pr ogrammed tone is set on the output. programming the bits 0 to 12 to "0" puts the tx into powersave and the output goes to v bias . powersave is also achieved by disabling the subaudio tx and the ctcss f ast detect (bits 7 and 5 in the signalling control register $80). the selcall transmitter is enabled with bit 2 in the signalling control register ($80). the tx frequency is set using bit 0 to bit 12 in the selcall tx register ($8d) using the formula below: a f (hz) 4 x f (hz) xtal tone = where a is the binary number programmed into the 13 bits. when bit 7 (in the first 8 bits) is set to "1" the tone output is set at v bias or notone without regard to the number "a" programmed. when bit 7 is "0" the pr ogrammed tone is set on the output. programming the bits 0 to 12 to "0" puts the selcall tx into powersave and the output goes to v bias . powersave is also achieved by disabling the selcall tx enable (bit 2 in the signalling control register $80). the dcs transmitter is enabled by setting bit 7 to "1" in the signalling control register ($80) having already set bit 1 to "1" in the signalling set up register ($82). note that bit 0 of this signalling set up register is used to select either 23-bit or 24-bit mode.
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 21 d/828/4 the tx data is set in the dcs byte 3, dcs byte 2 and dcs byte 1 registers ($85, $86 and $87). note that the dcs transmitter produces an inverted output. when the signal is fed through the summing amp, in an inverting configuration, the correct polarity of the dcs signal will be restored (the modulator gain blocks do not invert). 1.6.3 receiver (ctcss/selcall decoder) the ctcss/selcall decoder should first be set up accordi ng to the desired characteristics. this entails setting the tone decoder mode bit 2 of the si gnalling set up register ($82), and setting the tone decoder bandwidth in the signalling set-up register ($82), also programming the centre frequencies of the desired tones in the rx tone program register ($84). (it can hold up to 15 different tones). any tone can be in any location. when the device is decoding, the tones are scanned in the sequence of their location, i.e. $0 first and $e last. once a tone is detected the remaining tones are not checked. therefore if two tones are clos e enough in frequency for their bandwidths to overlap then the one in the lowest location will be detected. the tone irq mask in the irq mask register ($8e) should also be set as required. the tone decoder enable in the signalling cont rol register ($80) should then be set to "1". whilst in the ctcss/selcall decoder mode the fast/p redictive detector may be enabled (see below) (bit 5 in the signalling control register $80). when the ctcss/selcall decoder detects a change in its present state an irq will be generated and bit 3 of the irq flag register ($8f) will indicate this. to reduce the likelihood of false or missed ctcss decodes, it is recommended that pre-emphasis and exte rnal audio pass-band filtering (300 to 3000hz, for example) be used in the tx path. the change that occurred can be read from bit 4 of the selcall and sub-audio status register ($81) and if a tone is indicated by these bits then t he number of that tone can be read from bits 3, 2, 1 and 0 of the same register. 1.6.4 receiver (ctcss fast/predictive detector) this is used for detecting, in the fastest possibl e time, that sub-audio tones are present on the rx channel. response time is optimised for s peed at the expense of frequency resolution. it can operate in parallel to the ctcss/selcall dec oder. it is enabled using bit 5 of the signalling control register ($80). it has an irq which may be unmasked with bit 2 of the irq mask register ($8e). the fast ctcss mode detect/predict ive bit 3 in the signalling set-up register ($82) allows for one of two alternatives in the fast mode. in detect mode it will detect any periodic tone in the sub-audio band and when in predictive mode it will detect specific tones determined by the frequency set in the ctcss tx/fast rx frequency register ($83) and the fixed predictive mode bandwidth. successful detection is indicated by t he ctcss fast irq flag bit 2 in the irq flag register ($8f), and the ctcss fast tone bit 6 in the selcall and sub-audio status register ($81). 1.6.5 receiver (dcs decoder) the incoming signal is matched with the dcs code pr ogrammed into the dcs byte 1/2/3 registers. when the dcs decoder is enabled, t he dcs decode/no decode flag in bit 7 of the selcall and sub-audio status register ($81) will be set if the dec ode is successful (3 or fewer errors). a ''0" flag indicates a failure to decode. this flag is updated for every bit of the incoming signal. in order to detect the dcs turn-off code (134hz) , the ctcss tone decoder should also be enabled and programmed with this value. once detected this will cause a ctcss tone decode interrupt; the receiver audio output should then be muted.
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 22 d/828/4 1.6.6 general purpose timer (gpt) this may be used in conjunction with the ctcss/selc all decoder to form part of the decode algorithm or as a timer for any other purpose. it has an 8-bit va lue in the general purpo se timer register ($8b) set in units of 1msec, an irq flag in bit 6 of t he irq flag register ($8f) and an irq mask in bit 6 of the irq mask register ($8e). 1.6.7 full duplex modes the only functions that must operate as half duplex are: dcs tx or dcs rx dcs tx or ctcss tx ctcss decode or selcall decode all other functions are totally independent and ther efore a full duplex ctcss or full duplex selcall along with many other combinations are possible.
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 23 d/828/4 1.6.8 tx / fast rx tone table : ctcss the following table lists the commonly used ctcss tones and the corresponding values for programming the transmitter frequency / fast predictiv e frequency register (hex address $83). freq. byte 1 byte 2 freq. byte 1 byte 2 freq. byte 1 byte 2 (hz) (hex) (hex) (hz) (hex) (hex) (hz) (hex) (hex) 67.0 e b1 114.8 8 93 186.2 5 49 69.3 e 34 118.8 8 49 189.9 5 2f 71.9 d b1 123.0 8 1 192.8 5 1b 74.4 d 3b 127.3 7 bc 196.6 5 2 77.0 c c9 131.8 7 78 199.5 4 ef 79.7 c 5a 136.5 7 36 203.5 4 d6 82.5 b ef 141.3 6 f7 206.5 4 c4 85.4 b 87 146.2 6 bc 210.7 4 ac 88.5 b 1f 151.4 6 80 218.1 4 83 91.5 a c2 156.7 6 48 225.7 4 5d 94.8 a 62 159.8 6 29 229.1 4 4c 97.4 a 1b 162.2 6 12 233.6 4 37 100.0 9 d8 167.9 5 dd 241.8 4 12 103.5 9 83 173.8 5 aa 250.3 3 ef 107.2 9 2f 179.9 5 79 254.1 3 e0 110.9 8 e0 183.5 5 5d 1.6.9 rx tone program tables : ctcss the following table lists the commonly used ctcss t ones together with the values for programming the ?rx tone program? register (hex address $84). n.b. the values for byte 1 and 2 below apply to tone address 0 only. these values will vary depending on the location they are programmed into. freq. byte 1 byte 2 freq. byte 1 byte 2 freq. byte 1 byte 2 (hz) (hex) (hex) (hz) (hex) (hex) (hz) (hex) (hex) 67.0 3 d8 114.8 6 c0 186.2 a c9 69.3 4 9 118.8 6 d1 189.9 b 8 71.9 4 1b 123.0 7 10 192.8 b 44 74.4 4 4e 127.3 7 50 196.6 b 83 77.0 4 83 131.8 7 c0 199.5 b 8a 79.7 4 94 136.5 8 2 203.5 b c9 82.5 4 cb 141.3 8 44 206.5 c 6 85.4 5 2 146.2 8 86 210.7 c 46 88.5 5 14 151.4 8 c9 218.1 c c3 91.5 5 4c 156.7 9 c 225.7 d 41 94.8 5 87 159.8 9 48 229.1 d 48 97.4 5 94 162.2 9 82 233.6 d 89 100.0 5 cb 167.9 9 c6 241.8 e 8 103.5 6 7 173.8 a b 250.3 e 88 107.2 6 45 179.9 a 84 254.1 e c7 110.9 6 82 183.5 a c2
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 24 d/828/4 1.6.10 tx tone program table : selcall the following two tables list commonly used selcall t onesets together with the values for programming the ?selcall tx? register ($8d). eea ccir freq. (hz) byte 1 (hex) byte 2 (hex) freq. (hz) byte 1 (hex) byte 2 (hex) 1981 01 fd 1981 01 fd 1124 03 81 1124 03 81 1197 03 4a 1197 03 4a 1275 03 17 1275 03 17 1358 02 e6 1358 02 e6 1446 02 b9 1446 02 b9 1540 02 8f 1540 02 8f 1640 02 67 1640 02 67 1747 02 41 1747 02 41 1860 02 1e 1860 02 1e 1055 03 bb 2400 01 a4 930 04 3c 930 04 3c 2247 01 c1 2247 01 c1 991 03 f9 991 03 f9 2110 01 de 2110 01 de zvei 1 zvei 2 freq. (hz) byte 1 (hex) byte 2 (hex) freq. (hz) byte 1 (hex) byte 2 (hex) 2400 01 a4 2400 01 a4 1060 03 b7 1060 03 b7 1160 03 65 1160 03 65 1270 03 1a 1270 03 1a 1400 02 d0 1400 02 d0 1530 02 93 1530 02 93 1670 02 5c 1670 02 5c 1830 02 27 1830 02 27 2000 01 f8 2000 01 f8 2200 01 ca 2200 01 ca 2800 01 68 885 04 73 810 04 dc 810 04 dc 970 04 0f 740 04 0f 885 04 73 680 05 ca 2600 01 84 970 04 0f
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 25 d/828/4 1.6.11 rx tone program table : selcall the following two tables list commonly used selcall t onesets together with the values for programming the ?rx tone program? register ($84) in each tone address location as shown. eea ccir tone address freq. (hz) byte 1 (hex) byte 2 (hex) freq. (hz) byte 1 (hex) byte 2 (hex) 0 1981 a a 1981 a a 1 1124 15 c3 1124 15 c3 2 1197 26 d 1197 26 d 3 1275 36 85 1275 36 85 4 1358 46 d1 1358 46 d1 5 1446 57 4d 1446 57 4d 6 1540 67 cb 1540 67 cb 7 1640 78 4b 1640 78 4b 8 1747 88 cd 1747 88 cd 9 1860 99 84 1860 99 84 10 1055 a5 51 2400 ac 44 11 930 b4 c4 930 b4 c4 12 2247 cb 83 2247 cb 83 13 991 d5 a 991 d5 a 14 2110 ea c5 2110 ea c5 zvei 1 zvei 2 tone address freq. (hz) byte 1 (hex) byte 2 (hex) freq. (hz) byte 1 (hex) byte 2 (hex) 0 2400 c 44 2400 c 44 1 1060 15 53 1060 15 53 2 1160 25 d2 1160 25 d2 3 1270 36 83 1270 36 83 4 1400 47 e 1400 47 e 5 1530 57 c8 1530 57 c8 6 1670 68 86 1670 68 86 7 1830 79 49 1830 79 49 8 2000 8a 42 2000 8a 42 9 2200 9b 43 2200 9b 43 10 2800 ae 46 885 a4 86 11 810 b4 14 810 b4 14 12 970 c4 d8 740 c3 c8 13 885 d4 86 680 d3 80 14 2600 ed 45 970 e4 d8
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 26 d/828/4 1.6.12 dcs code table the following table gives a list of dcs codes together with the corresponding values (in hex) which should be programmed into the dcs byte registers for a 23-bit dcs sequence. dcs code dcs byte 3 ($85) dcs byte 2 ($86) dcs byte 1 ($87) dcs code dcs byte 3 ($85) dcs byte 2 ($86) dcs byte 1 ($87) 023 76 38 13 315 6c 68 cd 025 6b 78 15 331 23 e8 d9 026 65 d8 16 343 29 78 e3 031 51 f8 19 346 3a 98 e6 032 5f 58 1a 351 0e b8 e9 043 5b 68 23 364 68 58 f4 047 0f d8 27 365 2f 08 f5 051 7c a8 29 371 15 88 f9 054 6f 48 2c 411 77 69 09 065 5d 18 35 412 79 c9 0a 071 67 98 39 413 3e 99 0b 072 69 38 3a 423 4b 99 13 073 2e 68 3b 431 6c 59 19 074 74 78 3c 432 62 f9 1a 114 35 e8 4c 445 7b 89 25 115 72 b8 4d 464 27 e9 34 116 7c 18 4e 465 60 b9 35 125 07 b8 55 466 6e 19 36 131 3d 38 59 503 3c 69 43 132 33 98 5a 506 2f 89 46 134 2e d8 5c 516 41 b9 4e 143 37 a8 63 532 0e 39 5a 152 1e c8 6a 546 19 e9 66 155 44 d8 6d 565 0c 79 75 156 4a 78 6e 606 5d 99 86 162 6b c8 72 612 67 19 8a 165 31 d8 75 624 0f 59 94 172 05 f8 7a 627 01 f9 97 174 18 b8 7c 631 72 89 99 205 6e 98 85 632 7c 29 9a 223 68 e8 93 654 4c 39 ac 226 7b 08 96 662 24 79 b2 243 45 b8 a3 664 39 39 b4 244 1f a8 a4 703 22 b9 c3 245 58 f8 a5 712 0b d9 ca 251 62 78 a9 723 39 89 d3 261 17 78 b1 731 1e 49 d9 263 5e 88 b3 732 10 e9 da 265 43 c8 b5 734 0d a9 dc 271 79 48 b9 743 14 d9 e3 306 0c f8 c6 754 20 f9 ec 311 38 d8 c9
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 27 d/828/4 1.7 performance specification 1.7.1 electrical performance absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. units supply (v dd - v ss ) -0.3 7.0 v voltage on any pin to v ss -0.3 v dd + 0.3 v current into or out of v dd and v ss pins -30 +30 ma current into or out of any other pin -20 +20 ma p4 package min. max. units total allowable power dissipation at tamb = 25c 1660 mw ... derating 16.6 mw/c storage temperature -55 +125 c operating temperature -40 +85 c d2 package min. max. units total allowable power dissipation at tamb = 25c 600 mw ... derating 6.0 mw/c storage temperature -55 +125 c operating temperature -40 +85 c d5 package min. max. units total allowable power dissipation at tamb = 25c 1490 mw ... derating 14.9 mw/c storage temperature -55 +125 c operating temperature -40 +85 c operating limits correct operation of the device outsi de these limits is not implied. notes min. max. units supply (v dd - v ss ) 3.0 5.5 v operating temperature -40 +85 c xtal frequency 4.0315968 4.0324032 mhz
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 28 d/828/4 operating characteristics for the following conditions unless otherwise specified: xtal frequency = 4.032mhz audio level 0db ref = 308mvrms at 1khz v dd = 3.3v to 5.0v, tamb = -40c to +85c. composite signal = 308mvrms at 1khz + 75mvrms noise + 31mvrms sub-audio signal noise bandwidth = 5khz band limited gaussian notes min. typ. max. units dc parameters at v dd = 3.3v i dd (all powersaved) 2 - 0.5 1.0 ma i dd (fast detect enabled) 2 - 0.7 2.5 ma i dd (rx operating - dcs, fast detect and ctcss or selcall) 2 - 1.0 4.5 ma i dd (tx operating - dcs or selcall or sub audio) 2 - 0.7 3.0 ma i dd (tx operating - dcs and selcall) 2 - 0.8 4.0 ma at v dd = 5v i dd (all powersaved) 2 - 1.0 1.5 ma i dd (fast detect enabled) 2 - 1.1 4.5 ma i dd (rx operating - dcs, fast detect and ctcss or selcall) 2 - 1.7 7.5 ma i dd (tx operating - dcs or selcall or sub audio) 2 - 1.2 6.0 ma i dd (tx operating - dcs and selcall) 2 - 1.3 6.5 ma "c-bus" interface input logic "1" 70% - - v dd input logic "0" - - 30% v dd input leakage current (logic "1" or "0") -1.0 - 1.0 a input capacitance - - 7.5 pf output logic "1" (i oh = 120a) 90% - - v dd output logic "0" (i ol = 360a) - - 10% v dd "off" state leakage current (vout = v dd ) 6 - - 10 a ac parameters tone decoder sensitivity (pure tone) 5 - -26.0 - db ctcss response time (composite signal) - 140 - ms de-response time (composite signal) - 145 - ms frequency range 60 - 253 hz selcall response time (good signal) - 14 - ms de-response time (good signal) - 22 - ms frequency range 625 - 3000 hz dcs decoder bit-rate sync time - 2 - edges sensitivity 1 58 - 116 mvp-p
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 29 d/828/4 notes min. typ. max. units ctcss detector - fast detect sensitivity (pure ctcss tone) 5 - -26.0 - db response time (composite signal) - 56.0 - ms frequency range 60.0 - 253 hz ctcss detector - fast predictive sensitivity (pure ctcss tone) 5 - -26.0 - db response time (composite signal) 7 - 37.0 - ms frequency range 60.0 - 253 hz decode bandwidth - 40.0 - hz ctcss encoder frequency range 60.0 - 253 hz tone frequency resolution - - 0.2 % tone amplitude tolerance 1 -1.0 - +1.0 db total harmonic distortion 9 - 2.0 - % selcall encoder frequency range 208 - 3000 hz tone frequency resolution - - 0.2 % tone amplitude tolerance 1 -1.0 - +1.0 db total harmonic distortion 9 - 2.0 - % dcs encoder bit rate - 134.4 - bits/s amplitude tolerance 1 -1.0 - +1.0 db amplitude 1 871 mvp-p audio band-pass filter passband 8 300 - 3000 hz passband gain (at 1.0khz) 8 - 0 - db passband ripple (w.r.t. gain at 1.0khz) 8 -2 - +0.5 db stopband attenuation 8 33.0 - - db residual hum and noise - -50.0 - dbp alias frequency - 63 - khz output impedances tx audio out, tx sub audio ) enabled 10 - 2.0 - k out and rx audio out ) disabled - 500 - k rx amp and summing amp open loop gain (i/p = 1mv at 100hz) - 70.0 - db unity gain bandwidth - 5.0 - mhz input impedance (at 100hz) 10 - - m output impedance (open loop) - 6.0 - k
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 30 d/828/4 notes min. typ. max. units transmitter modulator drives: mod.1 attenuator attenuation (at 0db) -0.3 0 0.2 db cumulative attenuation error (wrt attenuation at 0db) -1.0 - 1.0 db output impedance 3 - 600 - input impedance (at 100hz) - 15.0 - k mod.2 attenuator attenuation (at 0db) -0.3 0 0.2 db cumulative attenuation error (wrt attenuation at 0db) -0.6 - 0.6 db output impedance 3 - 600 - general purpose timer timing period range 1 - 255 ms count interval - 1 - ms xtal/clock input pulse width ('high' or 'low') 4 40.0 - - ns input impedance (at 100hz) 10.0 - - m gain (i/p = 1mvrms at 100hz) 20.0 - - db dac range 1 312.5 - 2500 mv step size 1 - 312.5 - mv step accuracy 1 -30.0 - +30.0 mv input impedance (compin) - 10 - m output impedance (compout) - 1 - k notes: 1. at v dd = 5.0v only. signal levels or currents are proportional to v dd . 2. at tamb = 25c, not including any current drawn from the device pins by external circuitry. 3. small signal impedance, at v dd = 5.0v and tamb = 25c. 4. timing for an external input to the xtal/clock pin. 5. with input gain components set as recommended in figure 2. 6. irqn pin. 7. from one tone to another tone. 8. see filter response (figure 3). 9. measured at mod1 or mod2 output. 10. subaudio, selcall and dcs.
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 31 d/828/4 frequency (hz) gain (db) -60 -50 -40 -30 -20 -10 0 10 10 100 1000 10000 100000 250hz 300hz 3khz figure 3 typical audio band-pass filter frequency response timing diagrams figure 4 "c-bus" timing
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 32 d/828/4 for the following conditions unless otherwise specified: xtal frequency = 4.032mhz, v dd = 3.3v to 5.0v, tamb = -40c to +85c. parameter notes min. typ. max. units t cse "cs-enable to clock-high" 2.0 - s t csh last "clock-high to cs-high" 4.0 - s t hiz "cs-high to reply output 3-state" - 2.0 s t csoff "cs-high" time between transactions 2.0 - s t nxt "inter-byte" time 4.0 - s t ck "clock-cycle" time 2.0 - s notes: 1. depending on the command, 1 or 2 bytes of command data are transmitted to the peripheral msb (bit 7) first, lsb (bit 0) last. reply data is read from the peripheral msb (bit 7) first, lsb (bit 0) last. 2. data is clocked into and out of t he peripheral on the rising serial clock edge. 3. loaded commands are acted upon at the end of each command. 4. to allow for differing controller serial interface formats "c-bus" compatible ics are able to work with either polarity serial clock pulses.
ctcss/dcs/selcall processor fx828 ? 2009 cml microsystems plc 33 d/828/4 1.7.2 packaging figure 5 mechanical outline: order as part no. FX828D2 figure 6 mechanical outline: order as part no. fx828d5
ctcss/dcs/selcall processor fx828 handling precautions: this product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. cml does not assume any responsibility for the use of any circuitry described. no ipr or circu it patent licences are implied. cml reserves the right at any time without notice to change the said circuitry and this product specification. cml has a policy of test ing every product shipped using calibrated test equipment to ensure compliance with thi s product specification. specific testing of all circuit parameters is not necessarily performed. 1.7.2 packaging (continued) figure 7 mechanical outline: order as part no. fx828p4

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